(Not Applicable)
(Not Applicable)
The present invention relates generally to integrated circuit chip package technology, and more particularly to an integrated circuit chip package formed to include one or more singulation creases adapted to minimize occurrences of chipping and cracking during the chip package manufacturing process.
As is well known in the electrical arts, integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and a substrate such as a printed circuit board or PCB. The elements of the package typically include a metal lead frame, an integrated circuit die, a bonding material used to attach the integrated circuit die to the lead frame, bond wires which electrically connect pads on the integrated circuit die to respective, individual leads or contacts of the lead frame, and a hard plastic encapsulant material which covers the other components and forms the predominant portion of the exterior of the package.
In the chip package, the lead frame is the central supporting structure thereof. A conventional lead frame includes a die pad for accommodating the integrated circuit die, and a plurality of leads or contacts. In many varieties of integrated circuit chip packages, each bond pad provided on the die is wire-bonded to a respective contact, with portions of the contacts being exposed within the plastic encapsulant or package body and used to mount or electrically connect the chip package to the printed circuit board. In addition to portions of the leads or contacts being exposed, in certain chip packages, one surface of the die pad is also exposed for purposes of providing a thermally conductive path to dissipate heat from the integrated circuit die which is attached to the opposed surface of the die pad and is internal to the package, i.e., surrounded by the plastic encapsulant.
There is known in the prior art methodologies for simultaneously constructing a plurality of the above-described chip packages. In an exemplary methodology, a matrix of interconnected lead frames are etched into a lead frame strip. Subsequent to the attachment of the dies to respective ones of the die pads and electrical connection of the dies to respective ones of the contacts, an encapsulation step facilitates the application of an encapsulant material onto the surface of the lead frame strip to which the dies are attached. This encapsulation step covers the dies, the side surfaces of the die pads, and portions of the contacts within a single block of encapsulant material. The encapsulant material is then hardened, with a cutting step thereafter being used to separate individual chip packages from each other and from the disposable portions of each of the lead frames within the lead frame strip. The cutting step severs the connection between each of the interconnected lead frames within the lead frame strip, and the die pad and contacts of each individual lead frame. This cutting or xe2x80x9csingulationxe2x80x9d process is typically accomplished either via a punching process (punch singulation) or a sawing process (saw singulation).
With particular regard to a punch singulation process, one of the drawbacks associated with the use of this cutting process is the tendency for the hardened encapsulant material or package body of the chip package to chip or crack as a result of the punching operation. As will be recognized, such chipping or cracking of the chip package can result in the accelerated failure thereof as a result of, among other things, moisture permeation to the embedded integrated circuit die. The present invention addresses the chipping and cracking problem associated with the punch singulation process by forming pre-scores or creases in the package body of the chip package to provide a stress concentration line prior to the punch singulation process. The inclusion of this stress concentration line allows for smooth singulation along the singulation crease, thereby reducing stress on the edge of the chip package and avoiding the aforementioned chipping and cracking problems.
In accordance with the present invention, there is provided an integrated circuit chip package comprising a lead frame having an integrated circuit die electrically connected thereto. Partially encapsulating the lead frame and the die is a package body which includes a central portion circumvented by a peripheral portion defining opposed, generally planar top and bottom surfaces. Molded or formed into at least one of the top and bottom surfaces of the peripheral portion of the package body is a pre-score or singulation crease. It is contemplated that a single singulation crease may be disposed in the top surface of the peripheral portion of the package body, or that a pair of singulation creases may be disposed in respective ones of the top and bottom surfaces of the peripheral portion in opposed relation to each other. In the chip package, the lead frame includes a plurality of contacts and tie bars which extend within the peripheral portion of the package body, and are partially exposed within the bottom surface of the peripheral portion. It is contemplated that the bottom singulation crease of the pair may be collectively defined by a plurality of singulation crease segments disposed within the bottom surface of the peripheral portion and the exposed surfaces of the contacts and tie bars. In this regard, the lead frame is formed to include the singulation crease segments within prescribed surfaces of the contacts and tie bars. The singulation crease(s) are formed within the package body during its molding process, and are used to form a stress concentration line which allows for smooth singulation therealong, thus creating less stress on the edge of the chip package during the punch singulation process and avoiding the chip and crack problems discussed above.
The depth and cross-sectional configuration of the singulation crease(s) are variable. One presently contemplated cross-sectional configuration is wedge-shaped or triangular, with one contemplated depth of a single singulation crease formed in the top surface of the peripheral portion being approximately one-half of the thickness of the peripheral portion. In a chip package including an opposed pair of singulation creases, it is contemplated that the depth of such creases is such that a web is defined therebetween having a thickness which is approximately one-half of the thickness of the lead frame.
Further in accordance with the present invention, there is provided a method of forming an integrated circuit chip package. The method comprises the initial step of electrically connecting an integrated circuit die to a lead frame, and thereafter partially encapsulating the lead frame and the integrated circuit die with a package body having the above-described structural attributes and including the singulation crease(s). In the forming process, the package body is singulated along the singulation crease subsequent to being clamped in a manner wherein at least a portion of the singulation crease is exposed. If a single singulation crease is formed or molded into the top surface of the peripheral portion of the package body, the punch used in the punch singulation process will initially impact the top surface of the peripheral portion. Conversely, if an opposed pair of singulation creases are included in the peripheral portion, the punch will preferably initially impact the bottom surface of the peripheral portion. The initial impact on the top surface in the case of a single singulation crease being formed in the package body is to minimize the disturbance to the leads or contacts of the lead frame, portions of which are exposed within the bottom surface of the peripheral portion as indicated above.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.